Tighter layer to layer device overlay tolerances are needed in substrate processing (e.g., semiconductor device wafer processing) in order to meet device performance requirements and maximize the device yield. As circuit densities increase and device sizes decrease, pattern overlay is becoming one of the most significant performance issues during development of semiconductor process technology.
The manufacture of modern integrated circuit chips requires many different patterns to be layered one on another. Each new pattern has to be accurately registered with patterns already on the chip. The patterning tool (e.g., a scanner or stepper) that prints the pattern on the wafer contains subsystems that measure the location, height and tilt of the existing pattern. The time available to make these measurements is limited because these measurements have to be done while the previous wafer is being exposed (or otherwise processed). Consequently, the number of measurements that can be made during such time is limited.
According to the 2005 ITRS roadmap, at the 32-nm node, the overall budget for overlay accuracy on critical layers is expected to be approximately 5.7 nm 3σ. Scanners do adjust the leveling and alignment of each individual die before printing, but the leveling only corrects for average slopes in the X and Y directions (e.g., a tilted wafer plane) and not for vertical distortions on scale lengths shorter than a die. The alignment only compensates for some of the errors, but not all. To save time and improve throughput, scanners often perform alignment using some sample subset of the total number of die on a wafer, e.g., about 30 out of 150.
Complex distortions of the shape of the wafer in X, Y, and Z due to the non-uniform changes in geometry from previous processing steps are not adequately accounted for by the patterning tool. This tends to create regions of the wafer where yield is low due to poor alignment of one pattern with earlier patterns on chips in that area of the wafer. It is therefore necessary to inspect the wafers after patterning with a post-process analysis tool to ensure that the alignment is satisfactory.
One such type of metrology used is overlay metrology. Extensive technical literature can be found describing many different optical, algorithm and mark architectures which are relied on for this purpose. The current state of the art is, for example, the KLA-Tencor Archer 100 overlay metrology tool, which operates on the principle of high resolution bright field imaging of either box-in-box or periodic (AIM) two-layer metrology structures. With a box-in-box structure, the displacement between the centers of symmetry of two or more features, sequentially generated in a number of patterning steps is calculated by image processing of images acquired through a microscope and stored digitally. This technique is further described and analyzed by Neal T. Sullivan, “Semiconductor Pattern Overlay”, in Handbook of Critical Dimensions Metrology and Process Control, pp. 160-188, vol. CR52, SPIE Press (1993). Variations on such box-in-box structures are also described in U.S. Pat. Nos. 6,118,185 and 6,130,750, the disclosures of both of which are incorporated herein by reference.
A known alternative to the box-in-box technique is known as scatterometry overlay. In this technique, information is extracted from the intensity of light reflected from a periodic overlay mark. The overlay mark consists of gratings printed over gratings in subsequent patterning steps. In this approach, several overlay cells, with different intentional offsets between the two gratings of each cell, are formed in close proximity. The difference between the intensities of light scattered from these overlay marks allows a model-free determination of the overlay error. Such grating style targets (sometimes referred to as “AIM” marks) can be denser and more robust, than “box” or ring-type marks resulting in the collection of more process information, as well as target structures that can better withstand the rigors of chemical mechanical planarization (CMP). The use of such marks is described, e.g., by Adel et al. in commonly assigned U.S. Pat. Nos. 6,023,338, 6,921,916 and 6,985,618, all three of which are incorporated herein by reference for all purposes.
Overlay tools often use a mathematical model of the overlay process that takes into account errors caused by the scanner. There are two methodologies. One is to use data from the overlay tool to calculate higher order correctables and feed that back to the scanner. The other is for the scanner to calculate higher order correctables at alignment and use that to improve the model and improve overlay. Some examples of higher order shape correctables and how they are determined are described, e.g., in commonly-assigned U.S. Pat. No. 8,065,109 to Sathish Veeraraghavan et al., which is incorporated herein by reference. The higher order correctables calculated by the overlay tool may be subtracted from the overlay measurement data and the resulting values, known as residuals, provide a measure of how well the model used to calculate the correctables accounts for actual overlay errors.
Testing every die on a wafer is time consuming. As a result not all dies can be tested and a sampling plan must be created. The goal of a sampling plan is to identify the areas that are most likely to have problems with the alignment. The prior art method of generating a sampling plan includes sampling every die on a wafer and multiple wafers per lot for a given layer. The areas on the die that show the highest residuals over the entire sample set are then incorporated into a sampling plan that is then used for each subsequent wafer. The sampling plan is selected such that it optimizes the ability to calculate overlay residual errors and provide reasonable tool throughput and wafer cycle time. For example, a five point plan may select a die at the center of a wafer and die at four evenly spaced compass points about two thirds of the way out from the center. For a nine point plan, die located on diagonals may be added.
FIG. 1A depicts a typical sample plan that tests 24 fields per wafer for current 3X/2X nm nodes. The wafer 100 is divided into multiple dies 104. Out of all of the dies 104 on the wafer 100 only 24 dies are selected for further analysis. These 24 sample locations 105 are strategically spaced over the wafer such that they coincide with the areas that have shown the highest overlay residuals in the initial test wafers. This sampling plan is then used for all subsequent lots and only updated if significant overlay errors are seen in production.
However, it is understood in the art that overlay residual errors are often caused by changes in the wafer geometry. The wafer geometry caused by previous processes will change over time and these changes may occur in areas of the wafer that are not sampled in the original sampling plan. FIG. 1B provides a topographical map of the wafer geometry of a subsequent wafer 101 overlaid on the original sampling plan. By way of example and not by way of limitation, instead of using absolute measures of substrate geometry, FIG. 1B may also represent the change in geometry between a previous layer and the current layer (i.e., the delta of two geometry measurements on the same substrate). When matched up against the static sampling plan it is evident that there will be several areas where overlay residual errors are likely to occur, but will not be detected by the static sampling plan. For example, at location 107 there is a contour line between two regions. However, under the static sampling plan, there is no sample 105 taken anywhere along the contour. Also, at location 108 there is a steep slope from the largest increase in elevation to the largest decrease in elevation over a little over the length of one die. With such a large change in geometry over such a small area, location 108 would ideally have more than one sample 105. The areas of greater change in geometry are likely sources of overlay residual errors, but they are not guaranteed to be checked. Only by chance will areas like location 106 have adequate sampling. Without checking these problem areas, many lots may pass through with only marginal overlay. These overlay problems may produce the need for significant amounts of rework, or even scrap.
Thus, there is a need in the art for a method and an apparatus that are capable of generating a dynamic sampling plan that targets areas of individual wafers that are predicted to have marginal overlay.